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thermoelectric cooler (tec) controller data sheet adn8831 rev. a information furnished by analog devices is b elieved to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. n o license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel : 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 C 2012 analog devices, inc. all rights reserved. features two integrated zero drift, rail - to - rail, chop amplifiers tec voltage and current operation monitoring programmable tec maximum voltage and current programmable tec current heating and cooling limits configur able pwm switching frequency up to 1 mhz power efficiency: > 90% temperature l ock i ndication optional i nternal or external clock source clock phase adjustment for multiple drop operation supports negative temperature coefficient ( ntc ) thermistors or positive temperature coefficient (ptc) resi st ance thermal detectors (rtds) 5 v typical and optional 3 v supplies s tandby and shutdown mode availability adjustable soft start feature 5 mm 5 mm 32- lead lfcsp applications thermoelectric cooler (tec) temperature control dwdm optical transceiver modules optical fib er amplifiers optical networking systems instrument s requiring tec temperature control general description the adn8831 is a monolithic tec controller. it has two inte - grated, zero drift, rail - to - ra il comparators, and a pwm driver. a unique pwm driver works with an analog driver to control external selected mosfets in an h - bridge. by sensing the thermal detector feedback from the tec, the adn8831 can drive a tec to settl e the programmable temperature of a laser diode or a passive component attached to the tec module. the adn8831 supports ntc thermistor s or positive tempera - ture coefficient ( ptc ) rtd s . the target temperature is set as an analog voltage input either from a dac or from an external resistor divider driven by a reference voltage source . a proportional integral differential ( pid ) compensation network helps to quickly and accurately stabilize the adn8831 thermal control loop. an adjustable pid compensation network example is described in the an - 695 application note , using the adn8831 tec controller evaluation board . a typical reference voltage of 2.5 v is available from the adn8831 for thermistor temperature sensing or for tec voltage/current measuring and limiting in both cooling and heating modes. functional b lock diagram amplifier chop2 amplifier chop1 in1p in1n out1 in2p in2n out2 limiter/monitor ref soft start shutdown oscillator tmpgd vref ss/sb phase freq synci/sd linear mosfet driver pwm mosfet driver lfb lpgate lngate sfb spgate sngate compsw sw composc synco control ilimc ilim h itec vlim vtec cs 04663-001 figure 1.
adn8831 data sheet rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 detailed block diagram .................................................................. 3 specifications ..................................................................................... 4 electrical characteristics ............................................................. 4 absolute maximum ratings ............................................................ 6 thermal characteristics .............................................................. 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 11 oscillator clock frequency ....................................................... 12 oscillator clock phase ............................................................... 12 temperature lock indicator ..................................................... 13 soft start on power - up .............................................................. 13 shutdown mode ......................................................................... 13 standby mode ............................................................................. 13 tec voltage/current monitor ................................................. 13 maximum tec voltage limit .................................................. 13 maximum tec current limit ................................................. 14 applications information .............................................................. 15 signal flow .................................................................................. 15 thermistor setup ........................................................................ 15 thermistor amplifier (chop1) ................................................ 15 pid compensation amplifier (chop2) .................................. 16 mosfet driver amplifier ....................................................... 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 8/12 rev. 0 to rev. a changes to features and general description section s .............. 1 moved figure 2 ................................ ................................................. 3 changes to figure 2 .......................................................................... 3 changes to table 1 ............................................................................ 4 changes to table 2 and table 3 ....................................................... 6 changes to figure 3 and table 4 ..................................................... 7 changes to theory of operation section and figure 12 ........... 11 changes to figure 14 and figure 15 ............................................. 11 changes to oscillator clock frequency section and oscillator clock phase section ....................................................................... 12 changes to s oft start on power - up section , shutdown mode section , standby mode section , and tec voltage/current monitor section .............................................................................. 13 changes to figure 17 ...................................................................... 15 changes to pid compensation amplifier (chop2) section .... 16 changes to mosfet driver amplifier section and figure 21 .. 17 updated outline dimensions ....................................................... 18 changes to ordering guide .......................................................... 18 9/05 revision 0: initial version
data sheet adn8831 rev. a | page 3 of 20 detailed block diagr am adn8831 reference vb 1.25v 80k 2k 10k 8 7 6 5 4 3 2 1 ilimc in1p in1n out1 in2p in2n out2 32 31 30 29 28 27 26 25 24 22 21 18 17 16 15 14 12 11 10 9 temperature good 2.5v 20 19 compsw sfb pgnd sngate driver sw spgate pvdd composc soft start sb 250mv oscillator sd sd detect 13 itec ilimc ilimh 100k 100k 20k 20k lfb linear amplifier lpgate lngate lfb vb vc 23 vb g m 3 g m 2 g m 1 vc 20k 20k 20k 20k 1.25v 1.25v vb chop2 chop1 vb = 2.5v, v dd > 4.0v = 1.5v, v dd < 4.0v ilimh vlim vtec itec cs voltage limit 25k 20k 20k 5k sfb lfb 1.25v 1k 25k vref 04663-003 5k 1k avdd phase tmpgd agnd freq synco synci/sd ss/sb figure 2 . detailed block diagram
adn8831 data sheet rev. a | page 4 of 20 specifications electrical characteristics v dd = 3.0 v to 5.0 v, t a = 25c, unless otherwise noted. table 1. para meter 1 symbol test conditions /comments min typ max unit pwm output driver output transition time t r , t f c l = 3 300 pf 20 ns nonoverlapping clock delay 40 80 ns output resistance r o (sng ate, s pgate ) i l = 10 ma, v dd = 3.0 v 6 output voltag e swing 2 sfb v lim = vref 0 v dd v linear output amplifier output resistance r o, lngate i out = 2 ma, v dd = 3.0 v 200 r o, lpgate i out = 2 ma, v dd = 3.0 v 100 output voltage swing 2 lfb 0 v dd v power supp ly power supply voltage v dd 3.0 5.5 v supply current i sy pwm not switching 8 12 ma ?40c t a +85c 15 ma shutdown current i sd synci/ sd = 0 v 8 a soft start charging current i ss v ss = 0 v 8 a undervoltage lo ckout 3 uvlo low to high threshold 2.2 2.6 v standby current i sb synci/ sd = v dd , ss/ sb = 0 v 2 ma standby threshold v sb synci/ sd = v dd 150 200 mv error / compensation amplifiers input offset voltage v os1 v cm1 = 1.5 v, v in1p ? v in1m 10 100 v v os2 v cm2 = 1.5 v, v in2p ? v in2m 10 100 v input voltage range v cm1 , v cm 2 0 v dd v common - mode rejection ratio cmrr 1 , cmrr 2 v cm1 , v cm 2 = 0.2 v to v dd ? 0.2 v 120 db output voltage high v oh1 , v oh 2 v dd ? 0.03 v output voltage low v ol1 , v ol 2 25 mv power supply rejection ratio psrr 1 , psrr 2 3.0 v v dd 5.0 v 110 db output current i out1 , i out 2 sourcing and sinking 5 ma gain bandwidth product gbw 1 , gbw 2 v out = 0.5 v to (v dd ? 1 v) 2 mhz oscillator sync range f c lk synci/ sd connected to external clock 300 1 000 khz oscillator frequency f clk com posc = v dd , r freq = 118 k , s ynci/ sd = v dd , v dd = 5.0 v 800 1 000 1 250 khz nominal free - run oscillation frequency f clk - nominal c omposc = v dd , synci/ sd = v dd 200 1 000 khz phase adjustment rang e 2 clk v phase = 0.13 v, f synci/ sd = 1 mhz 50 d egree s v phase = 2.3 v, f synci/ sd = 1 mh z 330 d egree s phase adjustment default clk phase = open 180 d egree s reference voltage reference voltage v ref i ref = 2 ma 2.35 v i ref = 0 ma 2.37 2.47 2.57 v
data sheet adn8831 rev. a | page 5 of 20 para meter 1 symbol test conditions /comments min typ max unit logic controls logic low output voltage v ol tmpgd, synco, i out = 0 a 0 .2 v logic high output voltage v oh tmpgd, synco, i out = 0 a v dd ? 0.2 v logic low input voltage v il 0.2 v logic high input voltage v ih 3 v output high impedance v dd = 5.0 v 35 output low impedance v dd = 5.0 v 20 output high impedanc e v dd = 3.0 v 50 output low impedance v dd = 3.0 v 25 tec current measurement itec gain a v, itec (v itec C v ref /2) / (v lfb ? v cs ) 25 v/v itec output range high v itec, high no load v dd ? 0.05 v itec output range low v itec, low 0.05 v itec input range 2 v cs , v lfb 0 v dd v itec bias voltage v itec, b v lfb = v cs = 0 1.10 1.20 1.30 v maximum itec driving current i out, tec 1.5 ma tec voltage measurement vtec gain a v, vtec (v vtec C v ref /2 )/( v lfb ? v sfb ) 0.23 0.25 0.28 v/v vtec output range 2 v vtec v dd = 5.0 v 0.05 2.5 v vtec bias voltage 2 v vtec, b v lfb = v sfb = 0 v 1.20 1.25 1.35 v vtec output load resistance r vtec i vtec = 300 a 35 voltage limit vlim gain a v, lim (v lfb ? v sfb )/v vlim 5 v/v vlim input range 2 v vlim 0 v dd v vlim input current, cooling i vlim, cool v out2 < v ref /2 100 na vlim input current, heating i vlim, heat v o ut2 > v ref /2 i freq ma vlim input current accuracy, heating i vlim, heat i vlim /i freq 0.8 1.0 1.18 a/a current limit ilimc input voltage range v ilimc v ref /2 v dd ? 1 v ilimh input voltage range v ilimh 0.1 v ref /2 v ilimc limit threshold v th, il imc v itec = 2.0 v, r s = 20 m 1.98 2.0 2.02 v ilimh limit threshold v th, ilimh v itec = 0.5 v 0.48 0.5 0.52 v temperature good high threshold v out1, th1 in2m tied to out2, v in2p = 1.5 v 1.55 1.60 v low threshold v out1, th2 in2m tied to out2, v in2 p = 1.5 v 1.40 1.45 v 1 logic inputs meet typical cmos i /o conditions for source/sink current (~1 a) . 2 guaranteed by design or indirect test methods. 3 the adn8831 does not work when the supply voltage is less than uvlo.
adn8831 data sheet rev. a | page 6 of 20 absolute maximum ratings absolute maximum ratings at 25c, unless otherwise noted. table 2. parameter rating supply voltage 6 v input voltage gnd to v s + 0.3 v storage temperature range ?65c to +150c junction temperature 125c lead temperature (soldering, 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja jc unit 32-lead lfcsp (acpz) 33.4 1.02 c/w esd caution
data sheet adn8831 rev. a | page 7 of 20 pin configuration an d function description s notes 1. the lfcsp package has an exposed paddle that should be connected to agnd (pin 12) and the associated pcb ground plane. pin 1 indicator 1 ilimc 2 in1p 3 in1n 4 out1 5 in2p 6 in2n 7 out2 8vref 24 compsw 23 sfb 22 pgnd 21 sngate 20 sw 19 spgate 18 pvdd 17 composc 9 avdd 10 phase 11 tmpgd 12agnd 13freq 14 ss/sb 15 synco 16 synci/sd 32 ilimh 31 vlim 30 vtec 29 itec 28 cs 27 lfb 26 lngate 25 lpgate top view (not to scale) adn8831 04663-002 figure 3 . pin configuration table 4 . pin function descriptions pin no. mnemonic type description 1 ilimc analog input sets tec cooling current limit. 2 in1p analog input noninverti ng input to error amplifier. 3 in1 n analog input inverting input to error amplifier. 4 out1 analog output output of error amplifier. 5 in2p analog input noninverting input to compensation amplifier. 6 in2 n analog input inverting input to compensation a mplifier. 7 out2 analog output output of compensation amplifier. 8 vref analog output 2.5 v voltage reference output. 9 avdd power power for nondriver sections. 3.0 v minimum; 5.5 v maximum. 10 phase analog input sets synco clock phase relative to sync i/ sd clock. 11 tmpgd digital output logic output. active high. indicates when the out1 voltage is within 100 mv of in2p voltage. 12 agnd ground analog ground. connect to low noise ground. 13 freq analog input sets switching frequency with an external resistor. 14 ss/ sb analog input sets soft start time for output voltage. pull low (vtec = 0 v) to put the adn8831 into standby mode. 15 synco digital output phase adju stment clock output. phase set from phase pin. used to drive synci/ sd of other adn8831 devices. 16 synci/ sd digital input optional clock input. if not connected, clock frequency is set by freq pin. pull low to put the adn8831 into shutdown mode. pull high to negate shutdown mode. 17 composc analog output compensation for oscillator. connect to pvdd when in free - run mode, co nnect to r - c network when in external clock mode. 18 pvdd power power for output driver sections. 3.0 v minimum; 5.5 v maximum. 19 spgate analog output pwm output drives external pmos gate. 20 sw analog input connects to pwm fet drains. 21 sngate analo g output pwm output drives external nmos gate. 22 pgnd ground power ground. external nmos devices connect to pgnd. connect to digital ground. 23 sfb analog input pwm feedback. connect to the tec module negative ( ? ) terminal. 24 compsw analog input comp ensation pin for switching amplifier. 25 lpgate analog output linear output drives external pmos gate. 26 lngate analog output linear output drives external nmos gate. 27 lfb analog input linear feedback. connect to h - bridge transistor output and curre nt sense resistor . 28 cs analog input linear feedback. connect to the tec module positive (+) terminal. 29 itec analog output indicates tec current.
adn8831 da ta sheet rev. a | page 8 of 20 pin no. mnemonic type description 30 vtec analog output indicates tec voltage. 31 vlim analog input sets maximum voltage across tec modul e. 32 ilimh analog input sets tec heating current limit. 33 ep metal paddle at the back of package exposed pad. the lfcsp package has an exposed pad that should be connected to agnd (pin 12) and the associated pcb ground plate.
data sheet adn8831 rev. a | page 9 of 20 typical performance characteristics 04663-004 spgate sngate 10ns/div voltage (1v/div) t a = 25c v dd = 5v figure 4 . spgate and sngate rise time using circuit shown figure 12 04663-005 voltage (1v/div) spgate sngate t a = 25c v dd = 5v 10ns/div figure 5 . sngate and spgate fall time using circuit shown in fi gure 12 04663-006 0 0.4 0.8 1.2 1.6 2.0 2.4 0 60 120 180 240 300 360 v phase (v) phase shift (degrees) synci/sd = 1mhz t a = 25c v dd = 5v figure 6 . clock phase shift vs. phase voltage 04663-007 0 0 360 60 120 180 240 300 0.4 0.8 1.2 1.6 2.0 2.4 v phase (v) phase shift (degrees) synci/sd = 1mhz t a = 25c v dd = 3v figure 7 . clock phase shift vs. phase voltage 04663-008 ?40 ?15 10 35 60 2.465 2.485 85 2.470 2.475 2.480 temperature (c) v ref (v) v dd = 5v figure 8. v ref vs. temperature 04663-009 0 0 1000 1000 200 400 600 800 250 500 750 r freq (k ?) switching frequency (khz) v dd = 5v t a = 25c figure 9 . switching frequency vs. r freq
adn8831 da ta sheet rev. a | page 10 of 20 04663-010 ?40 640 740 85 660 680 700 720 ?15 10 35 60 temperature (c) switching frequenc y (khz) v dd = 5v figure 10 . switching frequency vs. temperature 04663-0 11 200 400 600 800 0 15 1000 3 6 9 12 switching frequenc y (khz) supply current (ma) v dd = 5v t a = 25c figure 11 . supply current vs. switching frequency
data sheet adn8831 rev. a | page 11 of 20 theory of operation the adn8831 is a single chip tec controller that sets and stabilize s a tec temperature. a voltage applied to the input of the adn8831 corresponds to a target tec temperature setpoint (tempset ). by controlli ng an external fet h - bridge, t he appropriate current is then applied to the tec to pump heat either to or away from an object attached to the tec. the objective temperature is measured with a thermal sensor attached to the tec and the sensed temperature (voltage) is fed back to the adn8831 to complete a closed thermal control loop of the tec. for best stability, the thermal sensor is to be closed to the object. in most laser diode modules, a tec and a ntc the rmistor are already mounted in the same package to regul ate the laser diode temperature . the adn8831 integrates two self - correcting , auto - zero amplifiers (chop1 and chop2). the chop1 amplifier usually takes a thermal sensor input and converts or regulates the input to a linear voltage output. the out1 (pin 4) voltage is proportional to the object temperature. the out1 (pin 4) voltage is fed into the compensation amplifier (chop2) and compared with a tempera - tur e setpoint voltage, creating an error voltage that is proportional to the difference. when u sing the chop2 amplifier, a pid network is recommended, as shown in figure 12 . adjusting the pid network optimizes the step response of the tec control loop . a compromised settling time and the maximum current ringing become available when this is done. details of how to adjust the compensation network are in the pid compensation amplifier (c hop 2) section. the tec is differentially driven in an h - bridge configuration. the adn8831 drives external mosfet transistors to provide the tec current . to further improve the power efficiency of the system, one side of the h - bridg e uses a pwm driver. only one inductor and one capacitor are required to filter out the switching frequency. the other side of the h - bridge uses linear output without requiring any additional circuitry. this proprietary configuration allows the adn8831 to provide efficiency of >90%. for most applica - tions, a 4.7 h inductor, a 22 f capacitor, and a switching frequency of 1 mhz , maintain less than 0.5% worst - case output voltage ripple across a tec. the maximum voltage across the tec and current fl ow ing through the tec is to be set using the vlim (pin 31) and ilim c (pin 1)/ilimh (pin 32) . additional details are in the maximum tec voltage limit section and the maximum tec current limit section . 04663-012 pgnd agnd tmpgd itec vtec in1n in2p out1 in1p ilimh ilimc vlim avdd vref pvdd 5? lpgate lfb lngate cs compsw sfb composc spgate synci/sd sw synco phase freq ss/sb sngate temp good indicator tec current output tec voltage output temperature set input 30.1k? 10f 27nf thermistor 10k? 10k? 10k? 10k? 10k? 10k? 17.8k? 8.2k? 8.2k? in2n out2 7.68k? 17.8k? 0.1f 0.1f 0.1f vdd 3.0v to 5.5v 0.1f 40f r sense 10k? 118k? 1k? 0.1f 3.3h 60f vdd tec nc nc nc = no connect figure 12 . typical application circuit 1
adn8831 da ta sheet rev. a | page 12 of 20 oscillator clock fre quency the adn8831 has an internal oscillator to generate the switching frequency for the output stage. this oscillator can be set in either free - run mode or synchronized to an ex ternal clock signal. free - run operation the switching frequency is set by a single resistor connected from freq (pin 13) to ground. table 5 shows r freq for some common switching frequencies. for free - run operation, connect synci / sd (pin 16) and composc (pin 17) to pvdd (pin 18) . table 5 . switching frequencies vs. r freq f switch r freq 250 khz 484 k 500 khz 249 k 750 khz 168 k 1 mhz 118 k higher switching frequencies reduce the voltage ripple across the tec . however, high switching frequencies create more power dissipation in the external transistors due to the more frequent charging and dis charging of the transistor gate capacitances. adn8831 composc freq syn ci/sd v dd v dd r freq 04663-013 figure 13 . free - run mode external clock operation the switching frequency of the adn8831 can be synchronized with an external clock. con nect the clock signal to synci/ sd (pin 16) and connect composc (pin 17) to an r - c network . this network compensates a pll to lock on to the external clock. adn8831 composc freq synci/sd 1m ? 04663-014 ext . clock source 1k ? 0.1 f 1nf figure 14 . synchronize to an external clock connecti ng multiple adn8831 devices connecting synco (p in 15) to the synci/ sd pin of another adn8831 allows for multiple adn8831 devices to work together using a single clock. multiple adn8831 devices can be driven from a single master adn8831 device , by connecting the synco pin of the master device to each slave synci/ sd pin, or by daisy - chain ing by connecting the synco pin of each device to the synci/ sd pin of the next device. when multiple adn8831 devices are clocked at the same frequency, the phase is to be adjusted to reduce power supply ripple. adn8831 master composc freq synci/sd v dd v dd 1 18k ? adn8831 slave composc freq 1m ? 1k ? 0.1 f 1nf v phase phase adn8831 slave composc freq 1m ? 1k ? 0.1 f 1nf v phase phase phase nc 10k ? v dd 04663-015 synco synci/sd synci/sd figure 15 . multiple adn8831 devices driven from a master clock o scillator clock phas e adjust the oscillator clock phase using a simple resistor divider at phase (p in 10) . phase adjustment allows two or more adn8831 devices to operate from the same clock frequency and not have all outputs switched simultaneously . this avoids the potential of an excessive power supply ripple. to ensure the correct operation of the oscillator, v phase is to remain in the range of 100 mv to 2.4 v. phase (pin 10) is internally biased at 1.2 v. i f phase (pin 10) remains open, the clock phase is set at 180 as the default.
data sheet adn8831 rev. a | page 13 of 20 temperature lock ind icator the tmpgd (pin 11) outputs a logic high when the out1 (pin 4) voltage reaches the in2p (pin 5) temperature setpoint (tempset) voltage. the tmpgd has a detection range of 25 mv and a 10 mv typical hysteresis. this allows direct interfacing either to the microcontrollers or to the supervisory circuitry. soft start on power - up the adn8831 can be programmed t o ramp up for a specified time after the power supply is turned on or afte r the sd pin is de asserted. this feature, called soft start, is useful for gradually increasing the duty cycle of the pwm amplifier. the soft start time is set with a single capacitor connected from ss (pin 14) to ground. the capacitor value is calculated by the following equation: ss ss c = 150 w h ere : c ss is the value of the capacitor in microfarads. ss is the soft start time in milliseconds. to set a soft start time of 15 ms , c ss is to equal 0.1 f. shutdown mode the shutdown mode sets the adn8831 into an ultralow current state. the current draw in shut down mode is typically 8 a. the shutdown input , sd (pin 16) , is active low. to s hut d ow n the device, drive sd to logic low. once a logic high is applied, the adn8331 is reactivated after the time delay set by th e soft start circuitry. refer to the soft start on power - up section for more details. standby mode the adn8831 has a standby mode that deactivates a mosfet driver stage. the current draw for the adn8831 in standby mode is less than 2 ma. the standby input ss/ sb (pin 14) is active low. after applying a logic high, the adn8331 reactivates following the delay. in s tandb y mode, only synco (pin 15) has a clock output. a ll the other function blocks are powered off . tec voltage/current monitor the tec real time voltage and current are detectable at vtec (p in 30) and itec (p in 29) , respectively. voltage monitor vtec (pin 30) is an analog voltage output pin with a voltage proportional to the actual voltage across the tec. a center vtec voltage of 1.25 v corresponds to 0 v across a tec. the output voltage is calculated using the following equation: )(25.0v25.1 sfb lfb vtec vv v ?+= curren t monitor itec (pin 29) is an analog voltage output pin with a voltage proportional to the actual current through the tec. a center itec voltage of 1.25 v corresponds to 0 a through the tec. the output voltage is calculated using the following equation: )(25v25.1 cs lfb itec vv v ?+= the equivalent tec current is calculated using the following equation: sense itec tec r v i ? = 25 v25.1 maximum tec voltage limit t he maximum tec voltage is set by applying a voltage at vlim (p in 31) to protect the tec. this voltage can be set with a resistor divider or a dac. the voltage limiter operates in bidirectional tec voltage, and cooling and heating voltage. using a dac both the cooling and heating voltage limits are set at the same levels when a voltage s ource directly drives vlim (p in 31) . the maximum tec voltage is calculated using the following equation: vlim maxtec v v = 5 )( w here : v tec (max) is the maximum tec voltage . v vlim is the voltage applied at vlim (pin 31) . using a resistor divider separate voltage limits are set using a resistor divider. the internal current sink circuitry connected to vlim (pin 31) draws a current when the adn8831 drives the tec in a heating direction , which lower s the voltage at vlim (pin 31) . the current sink is not active when the tec is driven in a cooling direction; therefore, the tec heating voltage limit is always lower than the cooling voltage limit. adn8831 vlim vlim freq r a r b r freq v ref i sink 04663-016 figure 16 . using a resistor divider
adn8831 da ta sheet rev. a | page 14 of 20 the sink current is set by the resis tor connected from freq (p in 13) to ground. the sink current is c alculate d using the following equation : freq sink r i v25.1 = w here : i sinc is the sink current at vlim (p in 31) . r freq is the resistor connected at freq ( pin 13) . the cooling and heating l imits are calculated using the following equations: b a b ref cool vlim rr rv v + = , b a sink cool vlim heat vlim rri v v ? = , , maximum tec current limit to protect the tec, separate maximum tec current limits in cooling and heating directions are set by applying a voltage at ilimc (p in 1) and ilimh (pin 32) . maximum tec currents are calculated using the following equations: sense ilimc cool maxtec r v i ? = 25 v25.1 ,, sense ilimh heat maxtec r v i ? = 25 v25.1 ,,
data sheet adn8831 rev. a | page 15 of 20 applications information 04663-017 chop1 ? + chop2 ? + in1p in2p in2n in1n out1 out2 17.68k? 7.68k? r x r fb r th (10k? @ 25c) v ref v ref /2 r 7 4 3 2 v tempset 5 6 v out1 v out2 z 1 z 2 tec lpf sfb spgate sngate lpgate lngate lfb pwm linear thermistor input amplifier a v = r fb /(r th + r x ) ? r fb /r pid compensator amplifier a v = z 2 /z 1 mosfet driver a v = 5 control figure 17 . signal flow block diagram signal flow the adn8831 integrates two auto - zero amplifiers defined as the chop1 amplifier and the chop2 amplifier. both of the amplifiers can be used as standalone amplifiers, th erefore , the implementation of temperature control ca n var y. figure 17 shows the signal flow through the adn8831 , and a typical implementation of the temperature control loop using the chop1 amplifier and the chop2 amplifier . in figure 17 , the chop1 amplifier and the chop2 amplifier are configured as the thermistor input amplifier and the pid compensation amplifier, respectively. the thermistor input amplifier gains the thermistor voltage then outputs to the pid compensation amplifier. the pid compensation amplifier then compensates a loop response over the frequency domain. the output from the compensation loop at out2 is fed to the linear mosfet gate driver. the voltage at lfb is fed with out2 into the pwm mosfet gate driver. including the external transistors, the gain of the differential output section is fixed at 5 . for details on the output drivers, see the mosfet driver amplifier section. thermistor setup the thermistor has a nonlinear relationship to temperature; near optimal linearity over a specified temperature range can be achieved with the proper value of r x placed in series with the thermistor. first, the resistance of the thermistor must be known, where high th high mid th mid low th low trr trr trr @ @ @ t low and t high are the endpoints of the temperature range and t mid is the average. in some case s, with only b constant available , r th is calculated using the following equation: r r th tt brr 11 exp where: r th is a resistance at t [k] . r r is a r esistance at t r [k]. r x is calculated using the following equation: mid high low high low high mid mid low x rrr rrrrrr r 2 2 thermistor amplifier (c hop 1) the chop1 amplifier can be used as a thermistor input amplifier . in figure 17 , the output voltage is a functio n of the thermistor temperature. the voltage at out1 is expressed as 2 1 ref fb x th fb out1 v r r rr r v u where: r th is a thermistor. r x is a compensation resistor. r is calculated using the following equation: c th x rrr 25 @ v out1 is centered around v ref /2 a t 25c. with the typical values shown in figure 17 , an average temperature-to - voltage coefficient is ? 25 mv/c at a range of +5c to +45c.
adn8831 data sheet rev. a | page 16 of 20 04663-018 ?15 5 25 45 0 2.5 65 0.5 1.0 1.5 2.0 temperature(c) v out1 (v) figure 18. v out1 vs. temperature pid compensation amplifier (chop2) use the chop2 amplifier as the pid compensation amplifier. the voltage at out1 feeds into the pid compensation amplifier. the frequency response of the pid compensation amplifier is dictated by the compensation network. apply the temperature set voltage at in2p. in figure 17, the voltage at out2 is calcu- lated using the following equation: ) ( tempset out1 tempset out2 vv z1 z2 vv ? ?? the user sets the exact compensation network. this network varies from a simple integrator to pi, pid, or any other type of network. the user also determines the type of compensation and component values because they are dependent on the thermal response of the object and the tec. one method for empirically determining these values is to input a step function to in2p, therefore changing the target temperature, and adjusting the compensation network to minimize the settling time of the tec temperature. a typical compensation network for temperature control of a laser module is a pid loop consisting of a very low frequency pole and two separate zeros at higher frequencies. figure 19 shows a simple network for implementing pid compensation. to reduce the noise sensitivity of the control loop, an additional pole is added at a higher frequency than the zeros. the bode plot of the magnitude is shown in figure 20. the unity-gain crossover frequency of the feedforward amplifier is calculated using the following equation: tecgain r3c1 f ?? ? ? 80 2 1 db0 to ensure stability, the unity-gain crossover frequency is to be lower than the thermal time constant of the tec and thermistor. however, this thermal time constant is sometimes unspecified making it difficult to characterize. there are many texts written on loop stabilization, and it is beyond the scope of this data sheet to discuss all methods and trade offs in optimizing compensation networks. adn8831 chop2 ? + in2p in2n 4 7 6 out1 out2 5 c1 cf c2 r2 r3 v t e m p s e t r1 04663-019 figure 19. implementing a pid compensation loop 04663-020 frequency (hz log scale) magnitude (log scale) 0db 1 2 r3c1 r1 r3 1 2 r3c2 1 2 r1c1 1 2 c2 (r2 + r3) r1 r2 || r3 figure 20. bode plot for pid compensation with an adn8831 -evalz board, an-695, an application note shows how to determine the pid network components for a stable tec subsystem performance.
data sheet adn8831 rev. a | page 17 of 20 mosfet driver amplif ier the adn8831 has two separate mosfet drivers: a switched output or pulse - width modulated (pwm) amplifier, and a high gain linear amplifier. each amplifier has a pair of outputs that drive the gates of external mosfets which, in turn, drive the tec as shown in figure 17 . a voltage across the tec is monitored via sfb (pin 23) and lfb (pin 27 ) . although both mosfet drivers achieve the same result, to provide constant voltage and high current, their operation is different . the exact equations for the two outputs are )25.1(40 ??= out2 b lfb vvv )25.1(5 ?+= out2 lfb sfb vvv w here : v out2 is the voltage at o ut2 (p in 7) . v b is determined by v dd as ]v0.4[v5.1 < = dd b v v ]v0.4[v5.2 > = dd b v v the voltage at out2 (pin 7) is determined by the compensation network that receives temperature set voltage and thermistor voltage fed by the input amplifier. v lfb has a low limit of 0 v and an upper limit of v dd . figure 21 shows the graphs of these equations. 0 2.5 5.0 lfb (v) 0 2.5 5.0 sfb (v) ?5.0 ?2.5 0 2.5 5.0 0 0.25 0.75 1.25 1.75 2.25 2.75 vtec (v) lfb-sfb 04663-021 out2 (v) figure 21 . out2 voltage vs. tec voltage
adn8831 data sheet rev. a | page 18 of 20 outline dimensions compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bottom view top view pin 1 indicator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r 3.25 3.10 sq 2.95 s eating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min figure 22. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADN8831ACPz-r2 ?40 ?c to +85 ?c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-7 ADN8831ACPz-reel7 ?40 ?c to +85 ?c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-7 adn8831-evalz ?40 ?c to +85 ?c evaluation board 1 z = rohs compliant part.
data sheet adn8831 rev. a | page 19 of 20 notes
adn8831 da ta sheet rev. a | page 20 of 20 notes ? 2005 C 2012 analog devices, inc. all rights reserved. trademarks and reg istered trademarks are the pro perty of their respective owners. d04663 -0- 8/12(a)

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